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d a t a sh eet objective speci?cation file under integrated circuits, ic02 1998 sep 11 integrated circuits saa7215 integrated mpeg avgd decoder
1998 sep 11 2 philips semiconductors objective speci?cation integrated mpeg avgd decoder saa7215 features general features integrated mpeg avgd decoder: audio, video and graphics decoding and digital video encoding 16-mbit or 32-mbit external sdram for mpeg audio and video decoding and graphics data storage single or double external synchronous dram (sdram) organized as 1 m 16 or 2 1m 16 (two independant 16-bit data bus) interfacing at 81 mhz. due to efficient memory use in mpeg decoding, more than 1 mbit is available for graphics in the single sdram configuration whereas 17 mbits are available in the double sdram configuration all basic operations of the avgd decoder are possible in both 16-mbit and 32-mbit configuration. enhanced performance is achieved by the use of 32-mbit external sdram. targeted to bskyb 3.0 and canal+ basic box and web box specifications fast 16-bit data + 22-bit address synchronous or asynchronous interface with external controller at up to 40.5 mhz dedicated input for compressed audio and video in pes or es in byte wide or bit serial format. accompanying strobe signals distinguish between audio and video data. transport stream error connection available. audio and/or video can also be input via the cpu interface in pes/es in 8 or 16-bit parallel format single 27 mhz or 40.5 mhz external clock for time base reference and internal processing. internal system time base at 90 khz can be synchronized via cpu port. all required decoding and presentation clocks are generated internally. flexible memory allocation under control of the external cpu enables optimized partitioning of memory for different tasks optimum compatibility with t-mips controller saa7214 boundary scan testing implemented external sdram self test supply voltage: 3.3 v; package: sqfp208. cpu related features 16-bit data, 22-bit address, chip select, data strobe and data acknowledge external control protocol fast 16-bit data + 22-bit address synchronous interface with the saa7214, at up to 40.5 mhz asynchronous interface possible with external microcontroller support of fast dma transfer flexible bidirectional interface to external sdram high speed/low latency interface with second graphics sdram byte access to the full sdram in the upper 16-mbit address range independent memory mapping of sdram and control registers two programmable independent interrupt lines available supports motorola 68xxx interfaces as well as lsi l64108 interface. mpeg2 system features parsing of mpeg-2 pes and mpeg-1 packet streams double system time clock counters stand-alone or supervised audio/video synchronization support for seamless time base change (edition) processing of errors flagged by channel decoding section. mpeg2 video features decoding of mpeg-2 video up to main level, main profile output picture format: ccir-601 4:2:2 interlaced pictures. picture format 720 576 at 50 hz or 720 480 at 60 hz support of constant and variable bit rates up to 15 mbits/s for the elementary stream digital video input/output interface on 8-bit, 27 mhz (c b yc r y multiplexed bus), at a ccir-656 format analog video output interface on both the rgb and y/c/cvbs formats horizontal and vertical pan and scan allows the extraction of a window from the coded picture flexible horizontal scaling from 0.5 up to 4 allows easy aspect ratio conversion including support for 2.21 : 1 aspect ratio movies. in case of shrinking an anti-aliasing pre-filter is applied. vertical scaling with fixed factors 0.5, 0.75, 1 or 2. factor 0.5 realizes picture shrink. factor 2 can be used for up-conversion of pictures with 288 (240) lines or less. factor 0.75 is used for letterbox presentation.
1998 sep 11 3 philips semiconductors objective speci?cation integrated mpeg avgd decoder saa7215 horizontal and vertical scaling can be combined to scale pictures to 1 4 of their original size, thus freeing up screen space for graphic applications like electronic program guides non full screen mpeg pictures can be displayed in a box of which position and background colour are adjustable by the external microcontroller. structured background is available as part of the graphic features. nominal video input buffer size for mp at ml 2.7-mbit video output may be slaved to internally (master) generated or externally (slave) supplied hv synchronization signals or ccir-656 contained synchronization signals. the position of active video is programmable. display phase is not affected by mpeg timebase changes. decoding and presentation can be independently handled under cpu control various trick modes under control of external microcontroller: C freeze field/frame on i- or p-frames; restart on i-picture C freeze field on b-frames; restart at any moment C scanning and decoding of i- or i- and p-frames in a ibp sequence C single step mode C repeat/skip field for time base correction C repeat/skip frame for display parity integrity. mpeg2 audio features decoding of 2 channel, layer i and ii mpeg audio. support for mono, stereo, intensity stereo and dual channel mode. constant and variable bit rates up to 448 kbits/s supported audio sampling frequencies: 48, 44.1, 32, 24, 22.05 and 16 khz crc error detection with automatic mute selectable output channel in dual channel mode storage of last 54 bytes in ancillary data field dynamic range control at output independent channel volume control and programmable inter channel crosstalk through a baseband audio processing unit muting possibility via external controller. automatic muting in case of errors. generation of beeps with programmable tone height, duration and amplitude support for up to 8 channels linear pcm elementary audio streams with 8, 16, 20 and 24 bits/sample and bit rates up to 6.144 mbits/s 96 khz lpcm samples will be mapped to a 48 khz multi-channel format volume control for linear pcm samples in three steps: - 6 db, - 12 db and - 18 db burst-formatting of ac-3 elementary streams (iec 1937) and mpeg-2 multi-channel streams in es or pes format for interconnection with an external multi-channel decoder via the digital audio output or the iec 958 output serial multi-channel digital audio output with 16, 18, 20 or 22 bits/sample, compatible either to i 2 s or japanese formats. output can be set to high impedance mode via the external controller. serial spdif (iec 958) audio output. output can be set to high-impedance mode. clock output 256 or 384f s for external da converter or clock input. output can be set to high-impedance mode. audio fifo in external sdram. programmable buffer size, at least 64-kbit is available. synchronization modes: pts controlled, pts free running, software controlled, buffer controlled pts register can be set via external controller. programmable processing delay compensation. graphics features graphics are presented in boxes independent of video format boxes can be up to full screen allowing double buffer display mechanism two independent graphics planes are available for background and/or graphics overlay two independent data paths with rgb 4 :4:4 and yc b c r 4:2:2 formats available with independent mixing rgb path transparent to yc b c r format screen arrangement of boxes is determined by display list mechanism which allows for multiple boxes, background loading, fast switching, scrolling, overlapping and fading of regions real-time anti-flickering performed in hardware. programmable hardware available for off-line anti-flickering hard edged or soft edged wiping of regions available
1998 sep 11 4 philips semiconductors objective speci?cation integrated mpeg avgd decoder saa7215 support of 2, 4, 8, 16-bit/pixel in fixed bit maps format or coded in accordance to the dvb variable/run length standard for region based graphics chrominance down-sampling filter switched per region display colours are obtained via colour look up tables (cluts) or directly from bitmap. clut output can be yc b c r t at 8-bit for each signal component thus enabling 16 m different colours and 6-bit for t which gives 64 mixing levels with video. clut output can also be rgbt with same resolutions. non linear processing available by means of luts. conversion matrices available to allow any format on any different data path (rgb or yc b c r ) map table mechanism to specify a sub set of entries if the clut is larger than required by the coded bit pattern. supported map tables are 16 to 256, 4 to 256 and 4 to 16. graphics boxes may overlap vertically even inside one graphics layer thanks to the use of flexible chained descriptors internal support for fast 3-d block moves in external sdram through data manipulation unit data manipulation unit allows format conversion and bit manipulation from a chained list of instructions graphics mechanism can be used for signal generation in the vertical blanking interval. useful for teletext, wide screen signalling, closed caption, etc. support for a single down loadable cursor of 1 k pixel with programmable shape. supported shapes are 8 128 pixels, 16 64 pixels, 32 32 pixels, 64 16 pixels and 128 8 pixels cursor colours obtained via two 16 entry cluts with yc b c r t at 6, 4, 4 respectively 2 bits and rgbt at 4, 4, 4 respectively 4 bits (or 4, 5, 3, respectively 4 bits). mixing of cursor with video and graphics in 4 levels. cursor can be moved freely across the screen without overlapping restrictions. teletext supported either with ttx-req/ttx interface, of by cpu loading of ttx data in sdram. applications the saa7215 integrated mpeg avgd decoder is aimed at being used in mpeg digital tv applications. this decoder is primarily designed to be connected to a saa7214 transport stream descrambler/demultiplexer/microcontroller by means of glueless interfaces even though connections to other market demultiplexers and/or microcontrollers are possible. the saa7215 can be used in any system where high-end graphics are needed (associated sdram can be extended to 32-mbit) as well as in low cost systems (all functions can be enabled with only 16-mbit of associated sdram). compatibility is also targeted with saa7217 and saa7219. general description this document is a reduced specification of the saa7215. the saa7215 is a mpeg2 source decoder which combines audio decoding and video decoding. additionally to these basic mpeg functions it also provides means for enhanced graphics, background display and/or on-screen display as well as encoding of output video. due to an optimized architecture for audio and video decoding, maximum capacity in external memory and processing power from the external cpu is available for graphics support.
1998 sep 11 5 philips semiconductors objective speci?cation integrated mpeg avgd decoder saa7215 quick reference data ordering information symbol parameter conditions min. typ. max. unit v dd supply voltage 3.0 3.3 3.6 v i dd(tot) total supply current v dd = 3.3 v - tbf - ma clk device clock input frequency (2 solutions are possible) - 30 ppm 27 +30 ppm mhz - 30 ppm 40.5 +30 ppm mhz type number package name description version SAA7215H sqfp208 plastic shrink quad ?at package; 208 leads (lead length 1.3 mm); body 28 28 3.4 mm sot316-1
1998 sep 11 6 philips semiconductors objective speci?cation integrated mpeg avgd decoder saa7215 block diagrams fig.1 block diagram. handbook, full pagewidth jtag fce107 memory interface 1 memory interface 2 16 mbit sdram (optional) 16 mbit sdram (compulsory) host interface video input buffer & synchronization video decoder system time base unit audio/video interface audio input buffer & synchronization audio decoder clock generation display unit graphics unit 2 digital video synchronization cursor unit digital encoder data manipulation unit audio dacs mpeg data clk digital video control data data graphics unit 1
1998 sep 11 7 philips semiconductors objective speci?cation integrated mpeg avgd decoder saa7215 fig.2 block diagram with preferred use in 16-mbit configuration. handbook, full pagewidth jtag fce108 memory interface 1 memory interface 2 16 mbit sdram host interface video input buffer & synchronization video decoder system time base unit audio/video interface audio input buffer & synchronization audio decoder clock generation display unit graphics unit 2 digital video synchronization cursor unit digital encoder data manipulation unit audio dacs mpeg data clk digital video analog control data graphics unit 1
1998 sep 11 8 philips semiconductors objective speci?cation integrated mpeg avgd decoder saa7215 fig.3 block diagram.with preferred use in 32-mbit configuration. handbook, full pagewidth jtag fce109 memory interface 1 memory interface 2 16 mbit sdram (graphics) 16 mbit sdram (mpeg) host interface video input buffer & synchronization video decoder system time base unit audio/video interface audio input buffer & synchronization audio decoder clock generation display unit graphics unit 2 digital video synchronization cursor unit digital encoder data manipulation unit audio dacs mpeg data clk digital video analog video control data data graphics unit 1
1998 sep 11 9 philips semiconductors objective speci?cation integrated mpeg avgd decoder saa7215 pinning pin description table 1 general purpose pins table 2 av interface pins table 3 digital audio interface pins table 4 digital video interface pins symbol pin count description i/o activity clk 3 1 40.5 mhz or 27 mhz clock input i rising edge clk_bus 1 target coldfire a clock (33 mhz) i rising edge reset 1 hard reset input i low level symbol pin count description i/o activity av_data[7:0] 15 8 mpeg stream input port i direct level a_data 1 mpeg audio stream serial input port i low level audden 1 byte synchronization of the serial audio input a_data i high level a_strobe 1 audio data strobe for inputs av_data and a_data i prog. level v_strobe 1 video data strobe for input av_data i prog. level a_req 1 audio data request o/z prog. level v_req 1 video data request o/z prog. level error 1 ?ag for bitstream error i prog. level symbol pin count description i/o activity sd 6 1 serial audio data o/z direct level sck 1 serial audio clock o/z edge ws 1 word select o/z direct level wb 1 word begin o/z direct level spdif 1 digital audio output o/z direct level fsclk 1 256 or 384f s (audio sampling) i/o edge symbol pin count description i/o activity cp27 12 1 27 mhz video presentation clock o rising edge yuv[7:0] 8 yuv video input/ output at 27 mhz i/o direct level hs 1 horizontal synchronization i/o prog. level vs 1 vertical synchronization i/o prog. level grph 1 indicator for graphics information o/z high level
1998 sep 11 10 philips semiconductors objective speci?cation integrated mpeg avgd decoder saa7215 table 5 analog video interface pins table 6 sdram interface pins symbol pin count description i/o activity r 5 1 analog video: red - analog g 1 analog video: green - analog b 1 analog video: blue - analog y/cvbs 1 analog luminance/analog composite video - analog c/cvbs 1 analog chrominance/analog composite video - analog symbol pin count description i/o activity sdram_data1[15:0] 71 16 sdram data i/o direct level sdram_addr1[11:0] 12 sdram address o direct level sdram_ras1 1 sdram row address strobe o low level sdram_cas1 1 sdram column address strobe o low level sdram_we1 1 sdram write enable o low level sdram_udq1 1 sdram write mask o direct level cp81m 1 81 mhz sdram memory clock o edge cp81mext 1 81 mhz sdram clock return path i edge read_out1 1 read command out o low level read_in1 1 read command in i low level sdram_data2[15:0] 16 sdram data i/o direct level sdram_addr2[11:0] 12 sdram address o direct level sdram_ras2 1 sdram row address strobe o low level sdram_cas2 1 sdram column address strobe o low level sdram_we2 1 sdram write enable o low level sdram_udq2[1:0] 2 sdram write mask o direct level read_out2 1 read command out o low level read_in2 1 read command in i low level
1998 sep 11 11 philips semiconductors objective speci?cation integrated mpeg avgd decoder saa7215 table 7 cpu interface pins table 8 dac power pins table 9 test pins symbol pin count description i/o activity ttxrq/cpu_sel[1] 53 1 teletext data request/cpu data interface selection i/o direct level cpu_sel[0] 1 cpu data interface selection i level ttx 1 teletext data i direct level data[15:0] 16 cpu data interface i/o direct level siz[1:0] 2 size of data on bus data i direct level address[20:0] 21 cpu address interface i direct level cs sd / address[21] 1 chip select for sdram access/cpu address: bit 21 i low level cs rg 1 chip select for control register access i low level ds/ ts 1 data strobe/transfer start i low level r/ w 1 read/write i direct level dt ack/ t a 1 data acknowledge/transfer acknowledge o/z low level dma_req 1 dma request i/o prog. level dma_ack 1 dma acknowledge i prog. level dma_rdy 1 dma ready o/z prog. level dma_done 1 dma end i prog. level irq[1:0] 2 individually maskable interrupts o/z prog. level symbol pin count description i/o activity avdd1 7 1 analog supply -- avdd2 1 analog supply -- avdd3 1 analog supply -- idump1 1 analog sink -- idump2 1 analog sink -- rset 1 analog reference -- avss 1 analog supply -- symbol pin count description i/o activity tdi 5 1 boundary scan test data input i direct level tdo 1 boundary scan test data output o/z direct level tms 1 boundary scan test mode select i direct level tck 1 boundary scan test clock i edge trst 1 boundary scan test reset i low level
1998 sep 11 12 philips semiconductors objective speci?cation integrated mpeg avgd decoder saa7215 table 10 global power pins symbol pin count description i/o activity v dd(co) 4 3.3 v supply for digital core logic -- v dd 11 3.3 v supply for pad ring -- v dd(an) 1 3.3 v supply for analog blocks(pll) -- v ss(co) 4 ground for core logic -- v ss 11 ground for pad ring --
1998 sep 11 13 philips semiconductors objective speci?cation integrated mpeg avgd decoder saa7215 application information fig.4 set-top box example. handbook, full pagewidth 16 21 ccir-656 audio dac 8 strobe 16 mbit sdram 13.5 mhz y/c/cvbs rgb irq 2 2 ts-in (pktdata) av data 40.5 mhz extension bus 16 mbit sdram (optional) addr addr ctrl ctrl ds data 16 12 4 5 12 data 16 data addr 8 2 3 uart pio hs, vs 2 6 1 grph dtack error 1 cp27 cs sd cs rg r/w i 2 c fce111 eprom saa7214 (t-mips) saa7215 mpeg-2avgd decoder dram flash
1998 sep 11 14 philips semiconductors objective speci?cation integrated mpeg avgd decoder saa7215 package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 0.40 0.25 3.70 3.15 0.25 0.25 0.13 0.23 0.13 28.1 27.9 0.5 30.9 30.3 1.45 1.05 8 0 o o 0.1 0.1 1.3 0.075 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.70 0.45 sot316-1 97-04-08 97-08-01 d (1) (1) (1) 28.1 27.9 h d 30.9 30.3 e z 1.45 1.05 d pin 1 index b p e q e a 1 a l p detail x l (a ) 3 b 52 c d h b p e h a 2 v m b d z d a z e e v m a x 1 208 157 156 105 104 53 y w m w m 0 5 10 mm scale 208 leads (lead length 1.3 mm); body 28 x 28 x 3.4 mm sqfp208: plastic shrink quad flat package; sot316-1 a max. 4.10
1998 sep 11 15 philips semiconductors objective speci?cation integrated mpeg avgd decoder saa7215 soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (order code 9398 652 90011). re?ow soldering reflow soldering techniques are suitable for all sqfp packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. wave soldering sqfp packages are not suitable for wave soldering, this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1998 sca60 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. middle east: see italy netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 319762, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 93 301 6312, fax. +34 93 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 5985 2000, fax. +46 8 5985 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. 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communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 160 1010, fax. +43 160 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 200 733, fax. +375 172 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 689 211, fax. +359 2 689 102 canada: philips semiconductors/components, tel. +1 800 234 7381 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. +45 32 88 2636, fax. +45 31 57 0044 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615800, fax. +358 9 61580920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 40 99 6161, fax. +33 1 40 99 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 23 53 60, fax. +49 40 23 536 300 greece: no. 15, 25th march street, gr 17778 tavros/athens, tel. +30 1 4894 339/239, fax. +30 1 4814 240 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: pt philips development corporation, semiconductors division, gedung philips, jl. buncit raya kav.99-100, jakarta 12510, tel. +62 21 794 0040 ext. 2501, fax. +62 21 794 0080 ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381 printed in the netherlands 545104/750/01/pp16 date of release: 1998 sep 11 document order number: 9397 750 04267

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